The semiconductor industry is truly amazing to keep up with the Moore’s Law for more than 45 years through new process and design technologies. In this talk, key challenges and opportunities of "More Moore" such as using computational/next-generation lithography for nano-patterning beyond 22nm and "More than Moore" such as using 3-dimensional (3D) through-silicon vias for heterogeneous 3D-IC integration will be discussed. Some recent results will be presented along with future research challenges and directions, e.g., on double patterning lithography layout decomposition and physical design, e-beam lithography throughput optimization, and 3D-IC TSV thermal-mechanical stress, electro-migration and reliability issues.

Biography

David Z. Pan is an Associate Professor (with tenure) and Director of the UT Design Automation (UTDA) Lab at the Department of Electrical and Computer Engineering, University of Texas at Austin. He received his Ph.D. in computer science (with honor) from UCLA in 2000 and was Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003 before joining UT. His research is mainly focused on nanometer physical design, design for manufacturing/reliability, intersection of physical and system-level co-design, and CAD for emerging technologies. He holds 8 U.S. patents and has published over 140 technical papers in premier journals and conference proceedings. He has served as an Associate Editor for IEEE Transactions on CAD, IEEE Transactions on VLSI, IEEE Transactions on CAS-I, IEEE Transactions on CAS-II, IEEE CAS Society Newsletter, and Journal of Computer Science and Technology. He has also served as the Chair of the IEEE CANDE Technical Committee, ACM/SIGDA Physical Design Technical Committee Chair, program committee member of major VLSI/CAD conferences, including DAC (subcommittee chair), ICCAD (subcommittee chair), ASPDAC (subcommittee chair), DATE, ISPD (Program/General Chair), ISCAS (CAD Chair), VLSI-DAT (EDA Chair), ISQED (subcommittee chair), ACISC (Program/General Chair), GLSVLSI (Publicity Chair), ISLPED (Exhibits Chair), SLIP (Publication Chair), and so on.  He is a member of the International Technology Roadmap for Semiconductor (ITRS).

 He has received a number of awards for his research contributions and professional services, including ACM/SIGDA Outstanding New Faculty Award, NSF CAREER Award, UCLA Engineering Distinguished Young Alumnus Award, IBM Faculty Award four times, SRC Inventor Recognition Award three times, 2010 IBM Research Pat Goldberg Memorial Best Paper Award in EE, CS and Math, Best Paper Awards from ISPD 2011, ASPDAC 2010, DATE 2009, ICICDT 2009, SRC Techcon 2007 and 1998, ACM Recognition of Service Award twice, ISPD 2007 Global Routing Contest Awards, eASIC Placement Contest Grand Prize (2009), and a number of Best Paper Award Nominations at premier conferences such as ASPDAC, DAC, ICCAD, and ISPD. He is an IEEE CAS Society Distinguished Lecturer for 2008–2009.